Regviz

Freescale Semiconductor /SKEAZN84 /SIM /PINSEL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as PINSEL

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Freescale Semiconductor/SKEAZN84/SIM/PINSEL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)I2C0PS 0 (0)SPI0PS 0 (0)UART0PS 0 (0)FTM0PS0 0 (0)FTM0PS1 0 (0)FTM2PS2 0 (0)FTM2PS3 0 (0)FTM0CLKPS 0 (0)FTM2CLKPS 0 (0)PWTCLKPS

FTM0CLKPS=0, FTM2PS3=0, SPI0PS=0, FTM2PS2=0, UART0PS=0, PWTCLKPS=0, FTM0PS1=0, FTM0PS0=0, I2C0PS=0, FTM2CLKPS=0

Description

Pin Selection Register

Fields

I2C0PS

I2C0 Port Pin Select

0 (0): I2C0_SCL and I2C0_SDA are mapped on PTA3 and PTA2, respectively.

1 (1): I2C0_SCL and I2C0_SDA are mapped on PTB7 and PTB6, respectively.
SPI0PS

SPI0 Pin Select

0 (0): SPI0_SCK, SPI0_MOSI, SPI0_MISO, and SPI0_PCS are mapped on PTB2, PTB3, PTB4, and PTB5.

1 (1): SPI0_SCK, SPI0_MOSI, SPI0_MISO, and SPI0_PCS are mapped on PTA6, PTA7, PTB1, and PTB0.
UART0PS

UART0 Pin Select

0 (0): UART0_RX and UART0_TX are mapped on PTB0 and PTB1.

1 (1): UART0_RX and UART0_TX are mapped on PTA2 and PTA3.
FTM0PS0

FTM0_CH0 Port Pin Select

0 (0): FTM0_CH0 channels are mapped on PTA0.

1 (1): FTM0_CH0 channels are mapped on PTB2.
FTM0PS1

FTM0_CH1 Port Pin Select

0 (0): FTM0_CH1 channels are mapped on PTA1.

1 (1): FTM0_CH1 channels are mapped on PTB3.
FTM2PS2

FTM2_CH2 Port Pin Select

0 (0): FTM2_CH2 channels are mapped on PTC2.

1 (1): FTM2_CH2 channels are mapped on PTC4.
FTM2PS3

FTM2_CH3 Port Pin Select

0 (0): FTM2_CH3 channels are mapped on PTC3.

1 (1): FTM2_CH3 channels are mapped on PTC5.
FTM0CLKPS

FTM0 TCLK Pin Select

0 (0): Selects TCLK1 for FTM0 module.

1 (1): Selects TCLK2 for FTM0 module.
FTM2CLKPS

FTM2 TCLK Pin Select

0 (0): Selects TCLK1 for FTM2 module.

1 (1): Selects TCLK2 for FTM2 module.
PWTCLKPS

PWT TCLK Pin Select

0 (0): Selects TCLK1 for PWT module.

1 (1): Selects TCLK2 for PWT module.

Links

()

Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data